Magnetic memories, particularly magnetic random access memories (MRAMs), have drawn increasing interest due to their potential for high read/write speed, excellent endurance, non-volatility and low power consumption during operation. An MRAM can store information utilizing magnetic materials as an information recording medium. One type of MRAM is a spin transfer torque random access memory (STT-RAM). STT-RAM utilizes magnetic junctions written at least in part by a current driven through the magnetic junction. A spin polarized current driven through the magnetic junction exerts a spin torque on the magnetic moments in the magnetic junction. As a result, layer(s) having magnetic moments that are responsive to the spin torque may be switched to a desired state. Further, multiple memory cells may be included in a single memory stack.
For example, FIG. 1 depicts a conventional multi-bit magnetic memory cell 10 as it may be used in a conventional STT-RAM. The conventional memory cell 10 stacks multiple conventional magnetic tunneling junctions (MTJs) 12 and 22. MTJ 12 includes a conventional antiferromagnetic layer 14, a conventional pinned layer 16 having magnetization 17, conventional tunneling barrier layer 18, and conventional free layer 20 having changeable magnetization 19. The MTJ 22 includes a conventional antiferromagnetic layer 24, a conventional pinned layer 26 having magnetization 27, conventional tunneling barrier layer 28, and conventional free layer 30 having changeable magnetization 29. The free layers 20 and 30 are the data storage layers. Stated differently, the free layers 20 and 30 have changeable magnetizations 19 and 29 the orientation of which determines the state of the memory MTJ 12 and 22, respectively. Each MTJ 12 and 22 is separated by a nonmagnetic, metallic spacer 21. Each MTJ 12 and 22 may also be considered to correspond to a separate magnetic memory cell. Also shown is conventional seed layer 11. The conventional memory stack might also include contacts (not shown) as well as a selection device (not shown), such as a transistor. In operation, the conventional MTJs/memory cells 12 and 22 are switched using different switching currents. Each conventional MTJ/memory cell 12 and 22 also has two stable states. Thus, the combination of the MTJs/memory cells 12 and 22 in the memory stack 10 may store two bits (e.g. logical states 00, 01, 10, and 11).
The conventional memory stack 10 is typically formed by depositing all of the layers 14, 16, 18, 20, 21, 24, 26, 28, and 30. A portion of the layers 14, 16, 18, 20, 21, 24, 26, 28, and 30 is covered by a mask and the MTJ 12 or 22 is defined. The mask is removed and another mask corresponding to the other MTJ 22 or 12 and the other MTJ 22 or 12 defined. For example, a mask covering a smaller area may be provided and the MTJ/memory cell 22 defined. A larger mask may then be provided and the MTJ/memory cell 12 defined.
Although the conventional memory stack 10 and MTJs 12 and 22 function, other methods for forming a multiple bit memory cell 22 are desired.